In response to increased demand for network capacity, wavelength division multiplexed (WDM) systems have been developed to increase the bandwidth of individual optical fiber networks. Such excess capacity must be managed, however, by directing or switching data to desired locations. Accordingly, high capacity switches have been developed to switch hundreds of gigabits per second to different optical fiber paths. In certain applications, however, multiple terabits of data must be switched. In which case, conventional switches may not have the required capacity to rapidly switch this much data.
To achieve even greater capacity, a distributed switching system is proposed whereby a distributed group of lower capacity switches are arranged in bays, each of which having one or more stages and appropriately coupled to one another to effectively function as a single high capacity switch. In order to properly route data through such a system, data is typically switched synchronously whereby data packets input to each stage are aligned with one another, output to a switch matrix, and supplied to desired outputs, where the data is fed to a subsequent stage or output from the system. Synchronized switching is often used with transmission protocols requiring data synchronization, such as the SONET (Synchronous Optical Network) protocol.
If the connections between stages in the distributed system are not substantially the same length, or components that make up the switch system do no t operate at the same speed, data may arrive at different times at the inputs to each switch stage, resulting in xe2x80x9cdata skew.xe2x80x9d If the received data is not properly synchronized, however, the data cannot be properly switched.
Consistent with the present invention, a distributed switching system is provided in order to achieve greater switching capacity. The distributed switching system includes a plurality of switches, each of which having a plurality of input buffers circuits, a switch matrix circuit and a skew adjustment circuit. Each of the plurality of input buffer circuits receives a respective one of a plurality of input data streams, and stores data associated with the data streams in selected buffer stages. The switch matrix and skew adjustment circuits are coupled to the input buffer circuits. Moreover, the skew adjustment circuit is configured to control the plurality of input buffer circuits to supply data respectively stored therein to the switch matrix circuit when an amount of the data stored in one of said plurality of input buffer circuits equals a predetermined amount.